package amd64

import (
	
	
)

// lowerConstant allocates a new VReg and inserts the instruction to load the constant value.
func ( *machine) ( *ssa.Instruction) ( regalloc.VReg) {
	 := .Return()
	 := .Type()

	 = .c.AllocateVReg()
	.insertLoadConstant(, )
	return
}

// InsertLoadConstantBlockArg implements backend.Machine.
func ( *machine) ( *ssa.Instruction,  regalloc.VReg) {
	.insertLoadConstant(, )
}

func ( *machine) ( *ssa.Instruction,  regalloc.VReg) {
	 := .Return()
	 := .Type()
	 := .ConstantVal()

	 := .Bits()
	if  < 64 { // Clear the redundant bits just in case it's unexpectedly sign-extended, etc.
		 =  & ((1 << .Bits()) - 1)
	}

	switch  {
	case ssa.TypeF32, ssa.TypeF64:
		.lowerFconst(, ,  == 64)
	case ssa.TypeI32, ssa.TypeI64:
		.lowerIconst(, ,  == 64)
	default:
		panic("BUG")
	}
}

func ( *machine) ( regalloc.VReg,  uint64,  bool) {
	if  == 0 {
		 := .allocateInstr().asZeros()
		.insert()
	} else {
		var  ssa.Type
		if  {
			 = ssa.TypeI64
		} else {
			 = ssa.TypeI32
		}
		 := .c.AllocateVReg()
		 := .allocateInstr().asImm(, , )
		.insert()

		 := .allocateInstr().asGprToXmm(sseOpcodeMovq, newOperandReg(), , )
		.insert()
	}
}

func ( *machine) ( regalloc.VReg,  uint64,  bool) {
	 := .allocateInstr()
	if  == 0 {
		.asZeros()
	} else {
		.asImm(, , )
	}
	.insert()
}