Package: github.com/klauspost/cpuid/v2

package cpuid Import Path github.com/klauspost/cpuid/v2 (on go.dev) Dependency Relation imports 8 packages, and imported by 2 packages

Involved Source Files d cpuid.go Package cpuid provides information about the CPU running the current program. CPU features are detected on startup, and kept for fast access through the life of the application. Currently x86 / x64 (AMD64) as well as arm64 is supported. You can access the CPU information by accessing the shared CPU variable of the cpuid library. Package home: https://github.com/klauspost/cpuid detect_x86.go featureid_string.go cpuid_amd64.s

Package-Level Functions (total 5)

func CombineFeatures(ids ...FeatureID) Features CombineFeatures allows to combine several features for a close to constant time lookup.

func Detect() Detect will re-detect current CPU info. This will replace the content of the exported CPU variable. Unless you expect the CPU to change while you are running your program you should not need to call this function. If you call this, you must ensure that no other goroutine is accessing the exported CPU variable.

func DetectARM() DetectARM will detect ARM64 features. This is NOT done automatically since it can potentially crash if the OS does not handle the command. If in the future this can be done safely this function may not do anything.

func Flags() Flags will enable flags. This must be called *before* flag.Parse AND Detect must be called after the flags have been parsed. Note that this means that any detection used in init() functions will not contain these flags.

func ParseFeature(s string) FeatureID ParseFeature will parse the string and return the ID of the matching feature. Will return UNKNOWN if not found.

Package-Level Variables (only one)

var CPU CPUInfo CPU contains information about the CPU as detected on startup, or when Detect last was called. Use this as the primary entry point to you data.

Package-Level Constants (total 268)

const ACRN Vendor = 28

const ADX FeatureID = 1 // Intel ADX (Multi-Precision Add-Carry Instruction Extensions) x86 features

const AESARM FeatureID = 205 // AES instructions ARM features:

const AESNI FeatureID = 2 // Advanced Encryption Standard New Instructions

const AMCC Vendor = 23

const AMD Vendor = 2

const AMD3DNOW FeatureID = 3 // AMD 3DNOW

const AMD3DNOWEXT FeatureID = 4 // AMD 3DNowExt

const Ampere Vendor = 14

const AMXBF16 FeatureID = 5 // Tile computational operations on BFLOAT16 numbers

const AMXCOMPLEX FeatureID = 11 // Matrix Multiplication of TF32 Tiles into Packed Single Precision Tile

const AMXFP16 FeatureID = 6 // Tile computational operations on FP16 numbers

const AMXFP8 FeatureID = 8 // Tile computational operations on FP8 numbers

const AMXINT8 FeatureID = 7 // Tile computational operations on 8-bit integers

const AMXTF32 FeatureID = 10 // Tile architecture

const AMXTILE FeatureID = 9 // Tile architecture

const AMXTRANSPOSE FeatureID = 12 // Tile multiply where the first operand is transposed

const Apple Vendor = 30

const APX_F FeatureID = 13 // Intel APX

const ARM Vendor = 15

const ARMCPUID FeatureID = 206 // Some CPU ID registers readable at user-level

const ASIMD FeatureID = 207 // Advanced SIMD

const ASIMDDP FeatureID = 208 // SIMD Dot Product

const ASIMDHP FeatureID = 209 // Advanced SIMD half-precision floating point

const ASIMDRDM FeatureID = 210 // Rounding Double Multiply Accumulate/Subtract (SQRDMLAH/SQRDMLSH)

const ATOMICS FeatureID = 211 // Large System Extensions (LSE)

const AVX FeatureID = 14 // AVX functions

const AVX10 FeatureID = 15 // If set the Intel AVX10 Converged Vector ISA is supported

const AVX10_128 FeatureID = 16 // If set indicates that AVX10 128-bit vector support is present

const AVX10_256 FeatureID = 17 // If set indicates that AVX10 256-bit vector support is present

const AVX10_512 FeatureID = 18 // If set indicates that AVX10 512-bit vector support is present

const AVX2 FeatureID = 19 // AVX2 functions

const AVX512BF16 FeatureID = 20 // AVX-512 BFLOAT16 Instructions

const AVX512BITALG FeatureID = 21 // AVX-512 Bit Algorithms

const AVX512BW FeatureID = 22 // AVX-512 Byte and Word Instructions

const AVX512CD FeatureID = 23 // AVX-512 Conflict Detection Instructions

const AVX512DQ FeatureID = 24 // AVX-512 Doubleword and Quadword Instructions

const AVX512ER FeatureID = 25 // AVX-512 Exponential and Reciprocal Instructions

const AVX512F FeatureID = 26 // AVX-512 Foundation

const AVX512FP16 FeatureID = 27 // AVX-512 FP16 Instructions

const AVX512IFMA FeatureID = 28 // AVX-512 Integer Fused Multiply-Add Instructions

const AVX512PF FeatureID = 29 // AVX-512 Prefetch Instructions

const AVX512VBMI FeatureID = 30 // AVX-512 Vector Bit Manipulation Instructions

const AVX512VBMI2 FeatureID = 31 // AVX-512 Vector Bit Manipulation Instructions, Version 2

const AVX512VL FeatureID = 32 // AVX-512 Vector Length Extensions

const AVX512VNNI FeatureID = 33 // AVX-512 Vector Neural Network Instructions

const AVX512VP2INTERSECT FeatureID = 34 // AVX-512 Intersect for D/Q

const AVX512VPOPCNTDQ FeatureID = 35 // AVX-512 Vector Population Count Doubleword and Quadword

const AVXIFMA FeatureID = 36 // AVX-IFMA instructions

const AVXNECONVERT FeatureID = 37 // AVX-NE-CONVERT instructions

const AVXSLOW FeatureID = 38 // Indicates the CPU performs 2 128 bit operations instead of one

const AVXVNNI FeatureID = 39 // AVX (VEX encoded) VNNI neural network instructions

const AVXVNNIINT16 FeatureID = 41 // AVX-VNNI-INT16 instructions

const AVXVNNIINT8 FeatureID = 40 // AVX-VNNI-INT8 instructions

const BHI_CTRL FeatureID = 42 // Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598

const Bhyve Vendor = 10

const BMI1 FeatureID = 43 // Bit Manipulation Instruction Set 1

const BMI2 FeatureID = 44 // Bit Manipulation Instruction Set 2

const Broadcom Vendor = 16

const Cavium Vendor = 17

const CETIBT FeatureID = 45 // Intel CET Indirect Branch Tracking

const CETSS FeatureID = 46 // Intel CET Shadow Stack

const CLDEMOTE FeatureID = 47 // Cache Line Demote

const CLMUL FeatureID = 48 // Carry-less Multiplication

const CLZERO FeatureID = 49 // CLZERO instruction supported

const CMOV FeatureID = 50 // i686 CMOV

const CMPCCXADD FeatureID = 51 // CMPCCXADD instructions

const CMPSB_SCADBS_SHORT FeatureID = 52 // Fast short CMPSB and SCASB

const CMPXCHG8 FeatureID = 53 // CMPXCHG8 instruction

const CPBOOST FeatureID = 54 // Core Performance Boost

const CPPC FeatureID = 55 // AMD: Collaborative Processor Performance Control

const CRC32 FeatureID = 212 // CRC32/CRC32C instructions

const CX16 FeatureID = 56 // CMPXCHG16B Instruction

const DCPOP FeatureID = 213 // Data cache clean to Point of Persistence (DC CVAP)

const DEC Vendor = 18

const EFER_LMSLE_UNS FeatureID = 57 // AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ

const ENQCMD FeatureID = 58 // Enqueue Command

const ERMS FeatureID = 59 // Enhanced REP MOVSB/STOSB

const EVTSTRM FeatureID = 214 // Generic timer

const F16C FeatureID = 60 // Half-precision floating-point conversion

const FCMA FeatureID = 215 // Floating point complex number addition and multiplication

const FHM FeatureID = 216 // FMLAL and FMLSL instructions

const FLUSH_L1D FeatureID = 61 // Flush L1D cache

const FMA3 FeatureID = 62 // Intel FMA 3. Does not imply AVX.

const FMA4 FeatureID = 63 // Bulldozer FMA4 functions

const FP FeatureID = 217 // Single-precision and double-precision floating point

const FP128 FeatureID = 64 // AMD: When set, the internal FP/SIMD execution datapath is no more than 128-bits wide

const FP256 FeatureID = 65 // AMD: When set, the internal FP/SIMD execution datapath is no more than 256-bits wide

const FPHP FeatureID = 218 // Half-precision floating point

const FSRM FeatureID = 66 // Fast Short Rep Mov

const Fujitsu Vendor = 19

const FXSR FeatureID = 67 // FXSAVE, FXRESTOR instructions, CR4 bit 9

const FXSROPT FeatureID = 68 // FXSAVE/FXRSTOR optimizations

const GFNI FeatureID = 69 // Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage.

const GPA FeatureID = 219 // Generic Pointer Authentication

const HLE FeatureID = 70 // Hardware Lock Elision

const HRESET FeatureID = 71 // If set CPU supports history reset and the IA32_HRESET_ENABLE MSR

const HTT FeatureID = 72 // Hyperthreading (enabled)

const HWA FeatureID = 73 // Hardware assert supported. Indicates support for MSRC001_10

const HYBRID_CPU FeatureID = 74 // This part has CPUs of more than one type.

const Hygon Vendor = 11

const HYPERVISOR FeatureID = 75 // This bit has been reserved by Intel & AMD for use by hypervisors

const IA32_ARCH_CAP FeatureID = 76 // IA32_ARCH_CAPABILITIES MSR (Intel)

const IA32_CORE_CAP FeatureID = 77 // IA32_CORE_CAPABILITIES MSR

const IBPB FeatureID = 78 // Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB)

const IBPB_BRTYPE FeatureID = 79 // Indicates that MSR 49h (PRED_CMD) bit 0 (IBPB) flushes all branch type predictions from the CPU branch predictor

const IBRS FeatureID = 80 // AMD: Indirect Branch Restricted Speculation

const IBRS_PREFERRED FeatureID = 81 // AMD: IBRS is preferred over software solution

const IBRS_PROVIDES_SMP FeatureID = 82 // AMD: IBRS provides Same Mode Protection

const IBS FeatureID = 83 // Instruction Based Sampling (AMD)

const IBS_FETCH_CTLX FeatureID = 92 // AMD: IBS fetch control extended MSR supported

const IBS_OPDATA4 FeatureID = 93 // AMD: IBS op data 4 MSR supported

const IBS_OPFUSE FeatureID = 94 // AMD: Indicates support for IbsOpFuse

const IBS_PREVENTHOST FeatureID = 95 // Disallowing IBS use by the host supported

const IBS_ZEN4 FeatureID = 96 // AMD: Fetch and Op IBS support IBS extensions added with Zen4

const IBSBRNTRGT FeatureID = 84 // Instruction Based Sampling Feature (AMD)

const IBSFETCHSAM FeatureID = 85 // Instruction Based Sampling Feature (AMD)

const IBSFFV FeatureID = 86 // Instruction Based Sampling Feature (AMD)

const IBSOPCNT FeatureID = 87 // Instruction Based Sampling Feature (AMD)

const IBSOPCNTEXT FeatureID = 88 // Instruction Based Sampling Feature (AMD)

const IBSOPSAM FeatureID = 89 // Instruction Based Sampling Feature (AMD)

const IBSRDWROPCNT FeatureID = 90 // Instruction Based Sampling Feature (AMD)

const IBSRIPINVALIDCHK FeatureID = 91 // Instruction Based Sampling Feature (AMD)

const IDPRED_CTRL FeatureID = 97 // IPRED_DIS

const Infineon Vendor = 20

const INT_WBINVD FeatureID = 98 // WBINVD/WBNOINVD are interruptible.

const Intel Vendor = 1

const INVLPGB FeatureID = 99 // NVLPGB and TLBSYNC instruction supported

const JSCVT FeatureID = 220 // Javascript-style double->int convert (FJCVTZS)

const KEYLOCKER FeatureID = 100 // Key locker

const KEYLOCKERW FeatureID = 101 // Key locker wide

const KVM Vendor = 6 // Kernel-based Virtual Machine

const LAHF FeatureID = 102 // LAHF/SAHF in long mode

const LAM FeatureID = 103 // If set, CPU supports Linear Address Masking

const LBRVIRT FeatureID = 104 // LBR virtualization

const LRCPC FeatureID = 221 // Weaker release consistency (LDAPR, etc)

const LZCNT FeatureID = 105 // LZCNT instruction

const Marvell Vendor = 25

const MCAOVERFLOW FeatureID = 106 // MCA overflow recovery support.

const MCDT_NO FeatureID = 107 // Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it.

const MCOMMIT FeatureID = 108 // MCOMMIT instruction supported

const MD_CLEAR FeatureID = 109 // VERW clears CPU buffers

const MMX FeatureID = 110 // standard MMX

const MMXEXT FeatureID = 111 // SSE integer functions or AMD MMX ext

const Motorola Vendor = 21

const MOVBE FeatureID = 112 // MOVBE instruction (big-endian)

const MOVDIR64B FeatureID = 113 // Move 64 Bytes as Direct Store

const MOVDIRI FeatureID = 114 // Move Doubleword as Direct Store

const MOVSB_ZL FeatureID = 115 // Fast Zero-Length MOVSB

const MOVU FeatureID = 116 // AMD: MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD

const MPX FeatureID = 117 // Intel MPX (Memory Protection Extensions)

const MSR_PAGEFLUSH FeatureID = 120 // Page Flush MSR available

const MSRIRC FeatureID = 118 // Instruction Retired Counter MSR available

const MSRLIST FeatureID = 119 // Read/Write List of Model Specific Registers

const MSVM Vendor = 7 // Microsoft Hyper-V or Windows Virtual PC

const NRIPS FeatureID = 121 // Indicates support for NRIP save on VMEXIT

const NSC Vendor = 5

const NVIDIA Vendor = 22

const NX FeatureID = 122 // NX (No-Execute) bit

const OSXSAVE FeatureID = 123 // XSAVE enabled by OS

const PCONFIG FeatureID = 124 // PCONFIG for Intel Multi-Key Total Memory Encryption

const PMU_FIXEDCOUNTER_CYCLES FeatureID = 233 PMU

const PMU_FIXEDCOUNTER_INSTRUCTIONS FeatureID = 235

const PMU_FIXEDCOUNTER_REFCYCLES FeatureID = 234

const PMU_FIXEDCOUNTER_TOPDOWN_SLOTS FeatureID = 236

const PMULL FeatureID = 222 // Polynomial Multiply instructions (PMULL/PMULL2)

const POPCNT FeatureID = 125 // POPCNT instruction

const PPIN FeatureID = 126 // AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled

const PREFETCHI FeatureID = 127 // PREFETCHIT0/1 instructions

const PSFD FeatureID = 128 // Predictive Store Forward Disable

const QEMU Vendor = 26

const QNX Vendor = 27

const Qualcomm Vendor = 24

const RDC Vendor = 13

const RDPRU FeatureID = 129 // RDPRU instruction supported

const RDRAND FeatureID = 130 // RDRAND instruction is available

const RDSEED FeatureID = 131 // RDSEED instruction is available

const RDTSCP FeatureID = 132 // RDTSCP Instruction

const RNDR FeatureID = 223 // Random Number instructions

const RRSBA_CTRL FeatureID = 133 // Restricted RSB Alternate

const RTM FeatureID = 134 // Restricted Transactional Memory

const RTM_ALWAYS_ABORT FeatureID = 135 // Indicates that the loaded microcode is forcing RTM abort.

const SBPB FeatureID = 136 // Indicates support for the Selective Branch Predictor Barrier

const SERIALIZE FeatureID = 137 // Serialize Instruction Execution

const SEV FeatureID = 138 // AMD Secure Encrypted Virtualization supported

const SEV_64BIT FeatureID = 139 // AMD SEV guest execution only allowed from a 64-bit host

const SEV_ALTERNATIVE FeatureID = 140 // AMD SEV Alternate Injection supported

const SEV_DEBUGSWAP FeatureID = 141 // Full debug state swap supported for SEV-ES guests

const SEV_ES FeatureID = 142 // AMD SEV Encrypted State supported

const SEV_RESTRICTED FeatureID = 143 // AMD SEV Restricted Injection supported

const SEV_SNP FeatureID = 144 // AMD SEV Secure Nested Paging supported

const SGX FeatureID = 145 // Software Guard Extensions

const SGXLC FeatureID = 146 // Software Guard Extensions Launch Control

const SGXPQC FeatureID = 147 // Software Guard Extensions 256-bit Encryption

const SHA FeatureID = 148 // Intel SHA Extensions

const SHA1 FeatureID = 226 // SHA-1 instructions (SHA1C, etc)

const SHA2 FeatureID = 227 // SHA-2 instructions (SHA256H, etc)

const SHA3 FeatureID = 228 // SHA-3 instructions (EOR3, RAXI, XAR, BCAX)

const SHA512 FeatureID = 229 // SHA512 instructions

const SiS Vendor = 12

const SM3 FeatureID = 230 // SM3 instructions

const SM3_X86 FeatureID = 151 // SM3 instructions

const SM4 FeatureID = 231 // SM4 instructions

const SM4_X86 FeatureID = 152 // SM4 instructions

const SME FeatureID = 149 // AMD Secure Memory Encryption supported

const SME_COHERENT FeatureID = 150 // AMD Hardware cache coherency across encryption domains enforced

const SPEC_CTRL_SSBD FeatureID = 153 // Speculative Store Bypass Disable

const SRBDS_CTRL FeatureID = 154 // SRBDS mitigation MSR available

const SRE Vendor = 29

const SRSO_MSR_FIX FeatureID = 155 // Indicates that software may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO.

const SRSO_NO FeatureID = 156 // Indicates the CPU is not subject to the SRSO vulnerability

const SRSO_USER_KERNEL_NO FeatureID = 157 // Indicates the CPU is not subject to the SRSO vulnerability across user/kernel boundaries

const SSE FeatureID = 158 // SSE functions

const SSE2 FeatureID = 159 // P4 SSE functions

const SSE3 FeatureID = 160 // Prescott SSE3 functions

const SSE4 FeatureID = 161 // Penryn SSE4.1 functions

const SSE42 FeatureID = 162 // Nehalem SSE4.2 functions

const SSE4A FeatureID = 163 // AMD Barcelona microarchitecture SSE4a instructions

const SSSE3 FeatureID = 164 // Conroe SSSE3 functions

const STIBP FeatureID = 165 // Single Thread Indirect Branch Predictors

const STIBP_ALWAYSON FeatureID = 166 // AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On

const STOSB_SHORT FeatureID = 167 // Fast short STOSB

const SUCCOR FeatureID = 168 // Software uncorrectable error containment and recovery capability.

const SVE FeatureID = 232 // Scalable Vector Extension

const SVM FeatureID = 169 // AMD Secure Virtual Machine

const SVMDA FeatureID = 170 // Indicates support for the SVM decode assists.

const SVMFBASID FeatureID = 171 // SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control

const SVML FeatureID = 172 // AMD SVM lock. Indicates support for SVM-Lock.

const SVMNP FeatureID = 173 // AMD SVM nested paging

const SVMPF FeatureID = 174 // SVM pause intercept filter. Indicates support for the pause intercept filter

const SVMPFT FeatureID = 175 // SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold

const SYSCALL FeatureID = 176 // System-Call Extension (SCE): SYSCALL and SYSRET instructions.

const SYSEE FeatureID = 177 // SYSENTER and SYSEXIT instructions

const TBM FeatureID = 178 // AMD Trailing Bit Manipulation

const TDX_GUEST FeatureID = 179 // Intel Trust Domain Extensions Guest

const TLB FeatureID = 224 // Outer Shareable and TLB range maintenance instructions

const TLB_FLUSH_NESTED FeatureID = 180 // AMD: Flushing includes all the nested translations for guest translations

const TME FeatureID = 181 // Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.

const TOPEXT FeatureID = 182 // TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX.

const Transmeta Vendor = 4

const TS FeatureID = 225 // Flag manipulation instructions

const TSA_L1_NO FeatureID = 183 // AMD only: Not vulnerable to TSA-L1

const TSA_SQ_NO FeatureID = 184 // AM onlyD: Not vulnerable to TSA-SQ

const TSA_VERW_CLEAR FeatureID = 185 // If set, the memory form of the VERW instruction may be used to help mitigate TSA

const TSCRATEMSR FeatureID = 186 // MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104

const TSXLDTRK FeatureID = 187 // Intel TSX Suspend Load Address Tracking

const UNKNOWN = -1 Keep index -1 as unknown

const VAES FeatureID = 188 // Vector AES. AVX(512) versions requires additional checks.

const VendorUnknown Vendor = 0

const VIA Vendor = 3

const VMCBCLEAN FeatureID = 189 // VMCB clean bits. Indicates support for VMCB clean bits.

const VMPL FeatureID = 190 // AMD VM Permission Levels supported

const VMSA_REGPROT FeatureID = 191 // AMD VMSA Register Protection supported

const VMware Vendor = 8

const VMX FeatureID = 192 // Virtual Machine Extensions

const VPCLMULQDQ FeatureID = 193 // Carry-Less Multiplication Quadword. Requires AVX for 3 register versions.

const VTE FeatureID = 194 // AMD Virtual Transparent Encryption supported

const WAITPKG FeatureID = 195 // TPAUSE, UMONITOR, UMWAIT

const WBNOINVD FeatureID = 196 // Write Back and Do Not Invalidate Cache

const WRMSRNS FeatureID = 197 // Non-Serializing Write to Model Specific Register

const X87 FeatureID = 198 // FPU

const XenHVM Vendor = 9

const XGETBV1 FeatureID = 199 // Supports XGETBV with ECX = 1

const XOP FeatureID = 200 // Bulldozer XOP functions

const XSAVE FeatureID = 201 // XSAVE, XRESTOR, XSETBV, XGETBV

const XSAVEC FeatureID = 202 // Supports XSAVEC and the compacted form of XRSTOR.

const XSAVEOPT FeatureID = 203 // XSAVEOPT available

const XSAVES FeatureID = 204 // Supports XSAVES/XRSTORS and IA32_XSS